Test Multiple Drives In Parallel

[jlee]

You seem to have some misconceptions about the reality of PCs on the marker.

No, I'm afraid you have it wrong. Today SATA and NVMe ports are connected via separate PCIe bus lanes into the main memory via an arbitration mechanism. Each drive has its own data path into main memory. Yes, they and the processor do share main memory, but main memory today has more than enough bandwidth to serve them all.

The USB bus does share devices, but modern USB versions beyond 3.0 use many of the low-level physical layer principles that PCIe does. Yes, you can hang enough drives on one USB port to max out its bandwidth, but with 10 Gbps and above USB is not the slow bus it once was. Most people just attach one external drive per USB port anyway.

This architecture is built into the north and south bridge chips, or in the single processor chip in laptops. It comes as part of the design of Intel and AMD processors and chipsets. As a result even the cheapest PCs today have enough bandwidth to run their supported storage devices at their full bandwidth simultaneously because it's built into the silicon. Of course cheaper PCs support fewer drives so their total bandwidth requirements aren't as great as higher-end PCs.

 

[PHolder]

@jlee I'm not going to argue with you, I know what I know, and I know you are taking a different perspective on it than I am. You would do well to understand this picture:

https://cdn.arstechnica.net/wp-content/uploads/archive/paedia/images/core-logic-southbridge.png

taken from:

PCI Express: An Overview

PCI Express has generated a lot of excitement in the PC enthusiast scene in a …

arstechnica.com

Getting a good picture to demonstrate the various cost cutting choices motherboard manufacturers have to make, and what sharing compromises that entails, is quite difficult because it's a case by case basis. Here's an older Intel one, for example: https://images.minitool.com/partiti...do-computers-work/how-do-computers-work-2.jpg

 

[jlee]

@jlee I'm not going to argue with you, I know what I know, and I know you are taking a different perspective on it than I am. You would do well to understand this picture:

https://cdn.arstechnica.net/wp-content/uploads/archive/paedia/images/core-logic-southbridge.png

You are looking at a block diagram which hides the actual implementation. The AHCI controller, for example, which controls the ATA bus, requires a PCIe connection to the host. It's in the standards document for the AHCI controller. Internally in the South Bridge silicon there is a PCIe bus connection to the AHCI controller.

The diagram is also way out of date. The front side bus, for example, was done away with around 2009.

For example, laptops don't even have North Bridge and South Bridge chips. Instead the function of both is combined into one chip, again with internal PCIe busses you won't see in any block diagram.