I have a hypothetical question about SpinRite.

[Lux Brush]

I've experienced and read about failures in the eMMC NAND storage of the Nintendo Wii U. That got me wondering if you could hypothetically run SpinRite on the NAND would that fix the type of failure that the NAND chips in the Wii U are experiencing? So, I thought I'd come here and see what you all think since you all have more experience with NAND and SpinRite than I ever will. I've been really curious about this hypothetical idea because of everything I've heard Steve talk about over the development of SpinRite 6.1.

 

[PHolder]

Flash memory has a limited number of writes per cell. It usually has a controller which tries to manage for this, and there are also over-provisioning of cells so that it is "wear leveled". When treated like a disk, each sector is numbered from 0 to n (the logical block address or LBA) so that you can refer back to it in things like directories, ect. So if the directory happens to be in a specific LBA, and is constantly being updated with new meta data (last access, for example), the controller will reorganize the flash blocks underneath such that the flash block number doesn't map one to one to the LBA. What this means, is that by the time write errors are occurring, if the flash controller has been working correctly, the write durability of all the flash blocks is used up, and the flash needs to be replaced/discarded.

 

[Lux Brush]

Flash memory has a limited number of writes per cell. It usually has a controller which tries to manage for this, and there are also over-provisioning of cells so that it is "wear leveled". When treated like a disk, each sector is numbered from 0 to n (the logical block address or LBA) so that you can refer back to it in things like directories, ect. So if the directory happens to be in a specific LBA, and is constantly being updated with new meta data (last access, for example), the controller will reorganize the flash blocks underneath such that the flash block number doesn't map one to one to the LBA. What this means, is that by the time write errors are occurring, if the flash controller has been working correctly, the write durability of all the flash blocks is used up, and the flash needs to be replaced/discarded.

Thank you for your reply. I thought of another question based on some other information about some of the problems Wii Us have been having. There's some anecdotal evidence that the problems seem to start occurring after the Wii U has been off and disconnected from power for a prolonged period of time. But the current evidence suggests that it's one of the three different manufacturers of eMMC that the Wii U had. The Hynix eMMC seems to be the most prone to the errors occurring. I wonder if Hynix did not do enough over-provisioning of cells, and that's why they are failing, or if there is some merit to the idea of them being off for a prolonged period of time? I seem to remember something about this type of memory settling from non-use, making it hard to read, though I have a terrible memory.

Thank you for entertaining my curiosity.

 

[PHolder]

Think of flash memory very loosely as a series of microscopic batteries. You put a charge in the cell, and it's supposed to stay trapped there for a long time. I suppose it's possible that a poor quality flash may develop a problem (leakage of the charge) over time if not "exercised"...

When you use flash memory in a system design, you usually have multiple components, such as the controller, a small amount of RAM for cache, and a bunch of flash chips. eMMC has to include all of this in one tiny chip. It's probably likely there is someone out there who has "cheaped" out their design (or someone crooked who is making bad quality stuff somehow in the timeframe of recently supply chain problems, for example.) In the early 2000's there was a problem with crappy capacitors that got into the supply chain... it may be possible that something like that happened to Nintendo with flash chips.